A. Field of the Invention
The invention relates generally to a method and apparatus for reducing the effects of parasitic bipolar discharge of silicon-on-insulator (SOI) electronic devices. More specifically, the invention relates to eliminating the unwanted effect of parasitic bipolar discharge of SOI field effect transistors (FET) in dynamic logic circuits.
B. Description of Related Art
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. Utilizing SOI technology designers can increase the speed of digital logic integrated circuits while reducing their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.
In recent years Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) integrated circuits and Complementary Metal Oxide Semiconductor (CMOS) FETs have gained popularity and are the most widely used type of integrated circuit technology. Today, CMOS electronic devices provide advantages of higher operating speeds, smaller size, lower power consumption, and are increasingly becoming cheaper to manufacture as a result of smaller component size, higher manufacturing production yields per semiconductor wafer, and larger wafer sizes. The most popular integrated circuit devices manufactured utilizing CMOS technology are microprocessors, memory, and digital logic circuits.
Traditional MOS and CMOS semiconductors consist of a metal on an oxide layer that is placed on a silicon substrate. The added impurities in the silicon substrate enable these devices to operate as transistors. On the other hand, SOI semiconductors include a thin layer of silicon placed on top of an insulator, such as silicon oxide or glass, and a MOS transistor built on top of this structure. The main advantage of constructing the MOS transistor on top of an insulator layer is to reduce the internal capacitance of the transistor. This is accomplished by placing the insulator oxide layer between the silicon substrate and the impurities required for the device to operate as a transistor. Reducing the internal capacitance of the transistor increases its operating speed. Therefore, with SOI technology faster MOS transistors can be manufactured resulting in higher performance semiconductors to fuel emerging needs for faster electronic devices.
SOI technology has several drawbacks. An inherent drawback of placing a MOS transistor on top of a SOI layer is that the MOS transistor is actually placed in parallel with a bipolar junction transistor. If enough current is passed through the MOS transistor, the parasitic bipolar transistor will turn on. This causes an unwanted effect called bipolar discharge and lowers the performance of the MOS transistor.
High speed CMOS circuits often employ a domino circuit technique that utilizes pre-charging to improve the gate speeds of the transistors. Dynamic circuit nodes are pre-charged during each clock cycle to a certain level. The problem with SOI FETs is that the parasitic bipolar transistor causes bipolar discharge. This is undesirable because it causes an unintended loss of charge on the drain nodes of the dynamic circuit.
Normally, parasitic bipolar action does not manifest itself in conventional, bulk, MOS transistors because the base of the bipolar transistor is always kept at ground potential, keeping the bipolar off. In SOI, the body of the MOS FET device, or base of the bipolar transistor, is floating and can be charged high by junction leakages induced when the drain and source terminals of the MOS FET are at a high potential. Subsequently, if the source is pulled to a low potential, the trapped charge in the base area is available as parasitic base current. The parasitic base current activates the bipolar transistor and generates a collector current at the drain terminal of the MOS FET. The unintentional loss of charge could lead to system failure, for example, by erroneously switching logic state.
It will be appreciated by those skilled in the art that a technique for eliminating parasitic bipolar discharge in MOS FET devices can be provided as discussed in U.S. patent application Ser. No. 09/240,244, filed Jan. 29, 1999, and entitled "Method And Apparatus For Elimination Of Parasitic Bipolar Action In Complementary Oxide Semiconductor (CMOS) Silicon On Insulator (SOI) Circuits," the disclosure of which is hereby incorporated herein by reference.
It will also be appreciated by those skilled in the art that a technique for eliminating parasitic bipolar discharge in logic circuits including CMOS SOI devices can be provided as discussed in U.S. patent application Ser. No. 09/240,991, filed Jan. 29, 1999, and entitled "Method And Apparatus For Elimination Of Parasitic Bipolar Action In Logic Circuits Including Complementary Oxide Semiconductor (CMOS) Silicon On Insulator (SOI) Elements," the disclosure of which is also hereby incorporated herein by reference.
The active discharging device effectively pre-discharges nodes in SOI MOS FET dynamic logic circuits to prevent the parasitic bipolar transistor from activating. However, in some embodiments of dynamic logic gates pre-discharging nodes is not always effective. Under certain input logic signal conditions a "sneak" bipolar leakage current path is created whenever intermediate nodes of the dynamic logic circuit are interconnected.
FIG. 3 illustrates a pre-discharged SOI domino logic circuit 44 that implements a logic function whose output may be determined according to: EQU OUT=NOT{(A+B)*(A1+B1)}.
FIG. 3 illustrates but one specific embodiment of a logic circuit. However, it will be appreciated by those skilled in the art that various implementations of logic functions and circuits such as AND, OR, NOR, NAND, EXCLUSIVE-OR, etc. and combinations thereof can be realized that have the characteristics in accordance with those illustrated in FIG. 3, namely a pre-discharged SOI domino logic circuit wherein a sneak current discharge path exists. Under certain states of logic inputs A, A1, B and B1, conductive path 66, located between nodes 48 and 50, may discharge transistors 68 or 64 to a circuit common node 62, or ground. In domino circuit 44, as illustrated in FIG. 3, the sneak path exists whenever input A is in a logic low state, B is in a logic high state and A1 and B1 are in logic low states. Given that the clock (CLK) has charged node 56 to a logic high state and is turned off, the sneak path exists from charge loss on node 56 to circuit common (ground) 62 via transistors 60 and 64. Since both A1 and B1 are in a logic low state the domino circuit 44 should not have "evaluated" or discharged node 56. Positive Channel-Field Transistors (PFETs) 64 and 68 were intended to discharge nodes 48 and 50, respectively to disable the bipolar effects of Negative Channel-Field Effect Transistors (NFETs) 58 and 60, respectively. Thus, it can be seen that since there is a conductive path 66 connecting intermediate nodes 48 and 50, the sneak path will provide a parasitic bipolar discharge path between intermediate nodes 48 and 50 of the dynamic logic circuit 44.
As a result, it can be seen that there is a need to minimize the effect of parasitic bipolar transistors in parallel with MOS transistors in dynamic logic circuits.
Moreover, it can also be seen that there is a need to eliminate parasitic bipolar action in dynamic logic circuits with at least one set of interconnected intermediate nodes that provide a current leakage path.